This patent application claims priority based on Japanese patent applications, H11-080118 filed on Mar. 24, 1999 and 2000-54335 filed on Feb. 29, 2000, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus and in particular to an A-D converter and a calibration unit incorporated in the semiconductor device testing apparatus.
2. Description of the Related Art
FIG. 1 is a block diagram showing a typical A-D converter 101, which converts an analog signal to a digital signal. The A-D converting apparatus 101 is comprised of an analog signal input portion 11, A-D converters 13a and 13b, a sampling clock signal generator 15, a reference clock signal generator 17, a delay circuit 24 and an interleave processing unit 19. The interleave processing unit 19 includes a multiplexer 29 and a memory unit 21.
An analog signal 50 is input to the analog signal input portion 11. The input analog signal 50 is sampled by the A-D converters 13a and 13b, which perform alternate sampling thereon, so as to be converted to a digital signal. The digital signals alternately output from the A-D converters 13a and 13b are put in a sequential order by the multiplexer 29, so as to be stored in a memory unit 21.
Based on a reference clock signal 54, the sampling clock signal generator 15 generates sampling clock signals 56a and 56b which alternately trigger the sampling operation of the A-D converters 13a and 13b. A delay circuit 24 calibrates the timing of the sampling operation of the A-D converters 13a and 13b, and i is arranged on a transfer path of the sampling clock signals 56a and 56b generated from the sampling clock signal generator 15.
FIG. 2 shows a readily available A-D converting apparatus 102 equipped with a plurality of analog signal portions. The A-D converting apparatus 102 includes A-D converters (13a, 13b, 13c, 13d) corresponding to a plurality of analog signal input portions (11a, 11b, 11c, 11d), respectively, a reference clock signal generator 17 and memory units (21a, 21b, 21c, 21d).
Respective analog signals (50a, 50b, 50c, 50d) are input to the respective analog signal input portions (11a, 11b, 11c, 11d). The input analog signals are converted to digital signals by the respective A-D converters (13a, 13b, 13c, 13d). The converted digital signals are stored in the memory units (21a, 21b, 21c, 21d).
FIG. 3A is a block diagram showing interleave processing. In interleave processing, sample data obtained from whichever of the two A-D converters 13a and 13b alternately sampling-operated, are put in sequential order by an interleave processing unit 19. By performing the interleave operation, sample data equivalent to a higher sampling rate than that of a single A-D converter is obtained. Referring to FIG. 3B, in interleave processing, the two A-D converters 13a and 13b are alternately triggered to sampling-operate, by supplying to the A-D converters two sampling clock signals 56a and 56b, whose respective phases are displaced from each other.
As mentioned above, interleave processing is a method by which digital signals output from a plurality of A-D converters are put in sequential order. In interleave processing, sampling sampling-operates, based on the sampling clock signal. However, in actuality, a time error occurs against a desired sampling clock, due to characteristic differences between respective A-D converters and those between the transfer paths of the sampling clock signal. Thus, calibration of the time error is necessary. As shown in FIG. 1, in the conventional practice, the time error is calibrated by providing a variable delay element in the midst of the path leading the sampling clock signals 56a and 56b to the respective A-D converters.
The conventional A-D converting apparatus 101 shown in FIG. 1 performs only the interleave process by which the A-D converters 13a and 13b are alternately sampling-operated. The A-D converting apparatus 101 cannot perform other processes.
In the conventional A-D converter 102 shown in FIG. 2, the A-D converter to be used for processing the analog signal input from each analog signal input portion is fixed in advance. Moreover, the delay circuit carries out calibration of the time error, making the calibration of the time error very complicated. Furthermore, the range in which the time error can be calibrated heavily depends on the performance of the delay circuit, so that high precision calibration cannot be performed.
Therefore, it is an object of the present invention to provide an A-D converting apparatus, a calibration unit and a semiconductor device testing apparatus and methods therefor to aid in solving at least one of the above disadvantages. These objects will be achieved by combining features described in the independent claims in the scope claims. Moreover, dependent claims provide further advantageous embodiments according to the present invention.
According to one aspect of the present invention, there is provided analog-to-digital (A-D) converting apparatus which samples an analog signal output from a semiconductor device under test to produce a digital signal, comprising: an analog signal input portion which inputs the analog signal; a plurality of analog-to-digital (A-D) converters which samples the analog signal input at said analog signal input portion, and convert the analog signal to the digital signal; a sampling clock signal generator which supplies either a synchronous sampling clock signal for use with an averaging process so as to sampling-operate the plurality of A-D converters in a synchronized manner, or an alternate sampling clock signal for use with an interleave process so as to alternately sampling-operate the plurality of A-D converters; an averaging processing unit which performs the averaging process on the digital signal output from the sampling-operated A-D converters, based on the synchronous sampling clock signal; and an interleave processing unit which interleaves the digital signal output from the sampling operated A-D converters, based on the alternate sampling clock signal.
The A-D converting apparatus may further comprise a mode specifying signal generator which generates a mode specifying signal which specifies either the averaging process or the interleave process, whereby either the averaging process unit or the interleave processing unit is selected based on the mode specifying signal.
Moreover, the A-D converting apparatus may further comprise a reference clock signal generator which generates a reference clock signal, wherein the sampling clock signal generator supplies the synchronous sampling clock signals synchronized with the reference clock signal to the respective A-D converters in the event that the averaging process is specified by the mode specifying signal while said sampling clock signal generator supplies the alternate sampling clock signal each having a different phase from other to said respective A-D converters in the event that the interleave process is specified by the mode specifying signal.
Moreover, the A-D converting apparatus may further comprise a plurality of memory units which store the digital signals output from the respective plurality of A-D converters, wherein the averaging processing unit and the interleave processing unit perform the averaging process and the interleave process, respectively, based on the digital signal stored in the plurality of memory units.
Suppose that there are a first A-D converter and a second A-D converter, the A-D converting apparatus may further comprise: an error calculation unit which calculates a time error which is a time displacement between a predetermined timing sampled by the second A-D converter against that sampled by the first A-D converter and an actual timing sampled by the second A-D converter; an error calibration value calculating unit which calculates a time error calibration value for use with calculation of calibrating the time error of the second A-D converter, based on the time error calculated by the error calculation unit; a read-out unit which reads the digital signal from the memory units which store the digital signal obtained by sampling a measured signal that is the analog signal to be measured; and an error calibrating unit which performs a calibration operation on the time error caused in the second A-D converter in the event of sampling the measured signal, based on the digital signal read out of said memory units by the read-out unit and the time error calibration value calculated by the error calibration value calculating unit.
According to another aspect of the present invention, there is provided analog-to-digital (A-D) converting apparatus comprising: an analog signal input portion which inputs the analog signal; an adder which adds up the digital signal output from a first A-D converter which sampling-operates the analog signal so as to be converted to the digital signal, and the digital signal output from a second A-D converter which sampling-operates the analog signal so as to be converted to the digital signal; a multiplexer which alternately inputs the digital signal output from the first A-D converter and the digital signal output from the second A-D converter so as to be sequentially output; and a selector which selects either an output value from said adder or an output value from said multiplexer.
According to still another aspect of the present invention, there is provided analog-to-digital (A-D) converting apparatus comprising: an analog signal input portion which inputs the analog signal; a plurality of analog-to-digital (A-D) converters which perform sampling operation on the analog signal input at the analog signal input portion, and convert the analog signal to the digital signal; and an analog signal distributor which distributes the digital signal to a single of or plurality of the A-D converters depending on a content of how the measured signal is converted to the digital signal.
Moreover, it is also preferable that a plurality of A-D converters are provided for the respective number of the corresponding plurality of analog signal input portions, and that the analog signal input from the single analog input portion is distributed to a plurality of the A-D converters.
Moreover, the A-D converting apparatus may further comprise: a sampling clock signal generator which supplies either a synchronous sampling clock signal for use with an averaging process so as to sampling-operate the plurality of A-D converters in a synchronized manner, or an alternate sampling clock signal for use with an interleave process so as to alternately sampling-operate the plurality of A-D converters; an averaging processing unit which performs the averaging process on the digital signal output from the sampling-operated A-D converters, based on the synchronous sampling clock signal; and an interleave processing unit interleaves the digital signal output from the sampling operated A-D converters, based on the alternate sampling clock signal.
Moreover, the A-D converting apparatus may further comprise: a mode specifying signal generator which generates a mode specifying signal which specifies either the averaging process or the interleave process, whereby either the averaging process unit or the interleave processing unit is selected based generator which supplies to the analog signal distributor a distribution control signal specifying that the analog signal be distributed to one of or plurality of said A-D converters, based on a process specified by the mode specifying signal.
According to still another aspect of the present invention, there is provided calibration apparatus which calibrates an error arising between a first A-D converter that performs sampling operation on an analog signal output from a semiconductor device so as to be converted to a digital signal and a second A-D converter that performs sampling operation on the analog signal so as to be converted to a digital signal, the calibration apparatus comprising: an error calculation unit which calculates a time error which is a time displacement between a predetermined timing sampled by the second A-D converter against that sampled by the first A-D converter and an actual timing sampled by the second A-D converter samples, based on sample data obtained by sampling a test signal for use in calculating the time error; an error calibration value calculating unit which calculates a time error calibration value for use with calculation of calibrating the time error of the second A-D converter, based on the time error calculated by the error calculation unit; a read-out unit which reads the digital signal from a memory unit which stores the sample data obtained by sampling a measured signal that is the analog signal to be measured; and an error calibrating unit which performs a calibration operation on the time error caused in the second A-D converter in the event of sampling the measured signal, based on the sample data read out of the memory unit by the read-out unit and the time error calibration value calculated by the error calibration value calculating unit.
In the calibration apparatus, it is desirable that the error calibrating unit performs discrete Fourier transformation on the sample data of the measured signal read out of the memory unit by the read-out unit, and calibrates the time error based on a discrete Fourier transformed value obtained from the discrete Fourier transformation and the time error calibration value.
Moreover, it is preferable that the error calculation unit calculates a gain and offset of the first and second A-D converters, and the error calibration value calculating unit includes: a gain calibration value calculating unit which calculates a gain calibration value of the first and second A-D converters; and an offset calibration value calculating unit which calculates an offset calibration value of the first and second A-D converters, and the error calibrating unit includes a gain-offset calibrating unit which calibrates the gain and offset of the first and second A-D converters, based on the sample data of the measured signal read out of the memory unit by the read-out unit, the gain calibration value and the offset calibration value.
In the calibration apparatus, it is preferable that the gain-offset calibrating unit performs a calibrating operation such that the gain calibration value is multiplied to the sample value of the measured signal sampled by the second A-D converter and then the offset calibration value is added.
According to still another aspect of the present invention, there is provided a method of calibrating an error arising between a first A-D converter which performs sampling operation on an analog signal to produce a digital signal so s to be converted to a digital signal and a second A-D converter which performs sampling operation on the analog signal so as to be converted to a digital signal, the error calibrating method comprising: calculating a time error which is a time displacement between a predetermined timing sampled by the second A-D converter against that sampled by the first A-D converter and an actual timing sample by the second A-D converter; calculating a time error calibration value for use with calculation of calibrating the time error, based on the time error; and calibrating the time error based on sample data obtained by sampling a signal to be measured and the time error calibration value.
Moreover, the method may further comprise: calculating an gain and offset of the first and second A-D converters; calculating gain calibration value and offset calibration value for use with calculation of calibrating the gain and offset, based on the gain and offset calculating by said calculating the gain and offset; and calibrating the gain and offset of the first and second A-D converters, based on the sample data obtained by sampling the signal to be measured, the gain calibration value and the offset calibrating value.
According to still another aspect of the present invention there is provided a recording medium which stores a program for calibrating a time error which is a time displacement between a predetermined timing sampled by the second A-D converter against that sampled by the first A-D converter and an actual timing sampled by the second A-D converter, wherein the program of the recording medium comprises: a first module for calculating the time error; a second module for calculating a time error calibration value for use with calculation of calibrating the time error of the second A-D converter based on the calculated time error; and a third module for calibrating the time error based on sample data obtained by sampling a signal to be measured and the time error calibration value.
Moreover, in the recording medium the program may further comprise: a fourth module for calculating gain and offset; a fifth module for calculating a gain calibration value for use in calibrating the gain and an offset calibration value for use in calibrating the offset, based on the gain and offset calculated by said fourth module; and a sixth module which calibrates the gain and offset of the first and second A-D converters, based on the sample data obtained by sampling the signal to be measured, the gain calibration value and the offset calibration value.
According to still another aspect of the present invention, there is provided semiconductor device testing apparatus for testing a semiconductor device that outputs an analog signal, comprising: a pattern generator which generates a semiconductor device input signal for testing the semiconductor device; a performance board which supplies to the semiconductor device the semiconductor device input signal output from said pattern generator; an analog signal input portion which inputs the analog signal output from the semiconductor device; a plurality of analog-to-digital (A-D) converters which perform sampling operation on the analog signal input at said analog signal input portion, and convert the analog signal to a digital signal; a sampling clock signal generator which supplies either a synchronous sampling clock signal for use with an averaging process so as to sampling-operate said plurality of A-D converters in a synchronized manner, or an alternate sampling clock signal for use with an interleave process so as to alternately sampling-operate said plurality of A-D converters; an averaging processing unit which performs the averaging process on the digital signal output from said sampling-operated A-D converters, based on the synchronous sampling clock signal; and an interleave processing unit which interleaves the digital signal output from the sampling operated A-D converters, based on the alternate sampling clock signal.
Moreover, in the semiconductor device testing apparatus, suppose that the plurality of A-D converters includes a first A-D converter and a second A-D converter, then it may further comprise: an error calculation unit which calculates a time error which is a time displacement between a predetermined timing sampled by the second A-D converter against that sampled by the first A-D converter and an actual timing sampled by the second A-D converter; an error calibration value calculating unit which calculates a time error calibration value for use with calculation of calibrating the time error of the second A-D converter, based on the time error calculated by said error calculation unit; a read-out unit, connected to said error calculation unit, which reads the digital signal from a memory unit which stores the digital signal obtained by sampling a measured signal that is the analog signal to be measured; and an error calibrating unit which performs a calibration operation on the time error caused in the second A-D converter in the event of sampling the measured signal, based on the sample data read out of the memory unit and the time error calibration value calculated by said error calibration value calculating unit.
This summary of the invention does not necessarily describe all necessarily features so that the invention may also be sub-combination of these described features.